NVIDIA Research's paper proposes a simpler, more energy-efficient GPU memory controller that drops most of the transaction sorting used by current designs.
PARE: Removes row-aware transaction sorting entirely. It stays close to a sorting controller on most workloads but loses ground in two bandwidth-sensitive kernels.
MS-PARE: Keeps only a narrow row-hit check to avoid that loss. Compared with the conventional sorting controller, it cuts area by 73.3% and average controller energy across 14 workloads by 55%.
Performance: The authors say it keeps near-parity performance with prior sorting controllers.
Context: The paper is for MICRO 2026, by researchers from NVIDIA and UC Berkeley, and argues that stacked 3D DRAM will make sorting controllers prohibitively large.
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NVIDIA Research's paper proposes a simpler, more energy-efficient GPU memory controller that drops most of the transaction sorting used by current designs.